This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A one-dimensional lattice of tunnel-diode oscillators is investigated for potential high-speed frequency divider. In the evolution of the investigated lattice, the high-frequency oscillation dominates over the low-frequency oscillation. When a base oscillator is connected at the end, and generates oscillatory signals with a frequency higher than that of the synchronous lattice oscillation, the oscillator output begins to move in the lattice. This one-way property guarantees that the oscillation dynamics of the lattice have only slight influence on the oscillator motion. Moreover, counter-moving pulses in the lattice exhibit pair annihilation through head-on collisions. These lattice properties enable an efficient frequency division method. Herein, the operating principles of the frequency divider are described, along with a numerical validation.

This paper presents a lumped-element Wilkinson power divider (WPD) using LC-ladder circuits composed of a capacitor and an inductor, and a series LR/CR circuit. The proposed WPD has only seven elements. As a result of designing the divider based on an even/odd mode analysis technique, we theoretically show that broadband WPDs can be realized compared to lumped-element WPDs composed of Π/T-networks and an isolation resistor. By designing the WPD to match at two operating frequencies, the relative bandwidth of about 42% can be obtained. This value is larger than that of the conventional WPD based on the distributed circuit theory. Electromagnetic simulation and experiment are performed to verify the design procedure for the lumped-element WPD designed at a center frequency of 922.5MHz, and good agreement with both is shown.

Recently, a multi-way TE10 mode power divider based on the TE10-TEp0 mode transducers consisting of a linearly arranged single-mode waveguide (SMWG) and an over-moded waveguide (OMWG) has been reported. However, the multi-way power divider based on the present mode transducer results in poor isolation and output matching characteristics. In this paper, an improvement of the isolation and the output matching characteristics is attempted by inserting the resistive sheets in the OMWG. It is shown that the isolation characteristics of about 20 dB are achieved by adjusting the dimensions of the resistive sheets. The validity of the design results is confirmed by an experiment.

In this paper, we propose a design method of compact multi-way Wilkinson power divider with a multiband operation for size reduction and band broadening. The proposed divider consists of multisection LC-ladder circuits in the division arms and isolation circuits between the output ports. To validate design procedures, we fabricated a trial divider at VHF band. The circuit layout of the trial divider was decided by using an electromagnetic simulator (Sonnet EM). Because the proposed divider consists of lumped element circuits, we can realize great miniaturization of a circuit area compared to that of the conventional Wilkinson power divider. The circuit size of the trial divider is 35 mm square. The measurement results for the trial divider by using a vector network analyzer indicates a relative bandwidth of about 60% under -17 dB reflection, flat power division within ±0.1 dB, and very low phase imbalances under 1.0 degree over the wide frequency range.

This paper proposes a multiway power divider for wideband (4:1) beamforming arrays. The divider's input reflection characteristic (S11) is achieved using a multisection stepped-impedance transformer. Moreover, the divider's isolation (S32) bandwidth is increased by incorporating inductors and capacitors in addition to the conventional resistor only isolation networks of the divider. The analysis of the proposed divider and comparison with the previous research model was conducted with four-way configuration. A prototype of a wideband eight-way power divider is fabricated and measured. The measured fractional bandwidth is about 137% from 1.3 to 6.8GHz with the -10dB criteria of input reflection (S11), output reflection (S22) and isolation (S32) simultaneously.

The high performance GaN power amplifier circuit operating at 7.1 GHz was demonstrated for potential use such as in a space ground station. First, the GaN HEMT chips were investigated for the high power amplifier circuit design. And next, the designed amplifier circuits matching with the load and source impedance of the non-linear models were fabricated. From measurement, the AB-class power amplifier circuit with the four-cell chip showed the power added efficiency (PAE) of 42.6% and output power with 41.7dBm at -3dB gain compression. Finally, the good performance of the power amplifier was confirmed in a 20-way radial power combiner with the PAE of 17.4% and output power of 52.6 dBm at -3dB gain compression.

In this paper, a novel multilayer substrate integrated waveguide (SIW) four-way out-of-phase power divider is proposed. It is realized by 3D mode coupling, on multilayer substrates. The structure consists of vertical Y-junction, lateral T-junction of SIW and lateral Y-junction of half-mode SIW. The advantages of the proposed structure are its low cost and ease of fabrication. Also, it can be integrated easily with other planar circuits such as microstrip circuits. An experimental circuit is designed and fabricated using the traditional printed circuit board technology. The simulated and measured results show that the return loss of the input port is above 15 dB over 8 to 11.8 GHz and transmissions are about -7.6±1.6 dB in the passband. It is expected that the proposed the proposed power divider will play an important role in the future integration of compact multilayer SIW circuits and systems.

Nearest-neighbor-search classifiers are attractive but they have high intrinsic computational demands which limit their practical application. In this paper, we propose a coprocessor for k (k with k≥1) nearest neighbor (kNN) classification in which squared Euclidean distances (SEDs) are mapped into the clock domain for realizing high search speed and energy efficiency. The minimal SED searching is carried out by weighted frequency dividers that drastically reduce the normally exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This also results in low power dissipation and high area-efficiency in comparison to the traditional method using large numbers of adders and comparators. The kNN classifier determines the class of an unknown input sample with a majority decision among the k nearest reference samples. The required majority-decision circuit is integrated with the clock-mapping-based minimal-SED searching architecture and proceeds with the classification immediately after identification of each of the k nearest references. A test chip in 180 nm CMOS technology, which can process 8 dimensions of 32 reference vectors in parallel, achieves low power dissipation of 40.32 mW (at 51.21 MHz clock frequency and 1.8 V supply voltage). Significantly, the distance search circuit consumes only 5.99 mW. Feature vectors with different dimensionality up to 2048 dimensions can be handled by the designed coprocessor due to a dimension extension circuit, enabling large flexibility for usage in different application.

In this paper, a 97-mW 8-phase CMOS voltage-controlled oscillator (VCO) and dividers covering the entire VCO oscillation range for a 134-GHz phase-locked loop (PLL) synthesizer are presented. The dividers have two injection-locked frequency dividers (ILFDs), one with and one without an inductor, and a pulse-swallowing counter with a differential dual-modulus prescaler. The VCO has a fundamental oscillation frequency range of 131.8 GHz to 134.3 GHz, achieved by controlling the back-gate voltage, which is also used to tune the locking range of divide-by-2 and divide-by-3 dividers. The ratio between the measured VCO oscillation frequencies and output frequencies of dividers is in good agreement with the target ratio. This indicates that the dividers covered the entire VCO oscillation range. We fabricated the VCO and dividers with a chip core area of 180 µm × 100 µm implemented in a 65-nm CMOS process. The total power consumption was 97 mW at a 1.2-V supply voltage.

Realization of a planar dual-band fork three-way power divider (PDBF3PD) with Cheng's equivalent structure is discussed. The Cheng's structure consists of two open-circuited stubs and a transmission line, and the characteristic impedances tend to be high. As a result, the realizable range of frequency ratios of upper frequency to lower frequency is limited in a narrow area. In this paper, an impedance scale factor is proposed to transform characteristic impedances into a realizable range and to facilitate the design of PDBF3PDs. Theoretical considerations are verified using a simulator of ADS2008U and by an experiment.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.

In this paper, we proposed that an area- and speed-effective fixed-point pipelined divider be used for reducing the bit-width of a division unit to fit a mobile rendering processor. To decide the bit-width of a division unit, error analysis has been carried out in various ways. As a result, when the original bit-width was 31-bit, the proposed method reduced the bit-width to 24-bit and reduced the area by 42% with a maximum error of 0.00001%.

A technique that enables a SSCG to fine-tune an output signal frequency and a spread ratio is presented. Proposed SSCG achieves the output signal frequency from 1.2 GHz to 3.0 GHz and the spread ratio from 0 to 30000 ppm. The fine-tuning technique achieves 30 ppm adjustment of the output signal frequency and 200 ppm adjustment of the spread ratio. This technique is achieved by controlling a triangular modulation signal characteristics generated by a proposed digital controlled wave generator. A proposed multi-modulus divider can have a divide ratio of 4/5 and 8/9. This SSCG has been fabricated in a 0.13-µm CMOS process. The output signal frequency-range and the spread ratio are achieved fluently from 0.1 to 3.0 GHz and from 0 to 30000 ppm, respectively. EMI noise is suppressed at less than 17.1 dB at the output signal frequency of 3.0 GHz and spread ratio of 30000 ppm.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

Based on the substrate integrated waveguide (SIW) technology, a new type of varactor-tuned radial power divider has been developed with a single bias supply. The varactors are used as tuning elements and allow for a frequency agile behavior. In addition, bandwidth characteristics have been analysed with group-delay. It has been measured with a single bias supply ranging from 6 V to 12 V that the center frequency of the power divider can be adjusted from 6.6 GHz to 7.2 GHz (600 MHz, 11.5%) while maintaining a low insertion loss (< 1 dB) in the passband.

In this paper, a novel design of planar dual-band multi-way lossless power dividers (PDs), namely Bagley Polygon PDs, is presented. The proposed PDs use Π-type dual-band transformers as basic elements, whose design formulas are analyzed and simplified to a concise form. The equivalent circuit of the dual-band Bagley Polygon PD is established, based on which design equations are derived mathematically. After that, the design procedure is demonstrated, and special cases are discussed. To verify the validity of the proposed design, 3-way and 5-way examples are simulated and fabricated at two IMT-Advanced bands of 1.8 GHz and 3.5 GHz, then simulation and measurement results are provided. The presented PDs have good performances on the bandwidths and phase shifts. Furthermore, the planar configuration leads to convenient design procedure and easy fabrication.

In this paper, we propose a wideband four-way turnstile-junction waveguide divider/combiner in the Ka-band. The proposed divider/combiner has an insertion loss of less than 0.8 dB over the frequency range of 28–39.5 GHz. A power combiner amplifier using this circuit and four MMIC amplifiers has been demonstrated with 83% combining efficiency at 34.9 GHz. The measured results show that the turnstile-junction waveguide divider-combiner is a suitable element for developing a broadband millimeter-wave spatial power combiner amplifier.