An adaptive algorithm for a single sinusoid detection using IIR bandpass filter with parallel block structure has been proposed by Nishimura et al. However, the algorithm has three problems: First, it has several input frequencies being impossible to converge. Secondly, the convergence rate can not be higher than that of the scalar structure. Finally, it has a large amount of computation. In this paper, a new algorithm is proposed to solve these problems. In addition, a new structure is proposed to reduce the amount of computation, in which the adaptive control signal generator is realized by the paralel block structure. Simulation results are given to illustrate the performance of the proposed algorithm.

This paper proposes an algorithm for the design of FIR digital filters whose coefficients have CSD representations. The total number of nonzero digits is specified. A set of filters whose frequency responses have less than or equal to a given Chebyshev error have their coefficients in a convex polyhedron in the Euclid space. The proposed algorithm searches points where a coefficient is maximum or minimum in the convex polyhedron by using linear programing. These points are connected whih the origin to make a convex cone. Then the algorithm evaluates CSD points near these edges of the cone. Moving along these edges means the scaling of frequency responses. The point where the frequency response is the best among all the candidates under the condition of specified total number of nonzero digits is selected as the solution. Several techniques are used to reduce the calculation time. Design examples show that the proposed method can design better frequency responses than the conventional methods.

The purpose of this paper is to provide a practical tool for performing a shift operation in orthonormal compactly supported wavelet bases. This translation τ of a discrete sequence, where τ is a real number, is suitable for filter bank implementations. The shift operation in this realization is neither related to the analysis filters nor to the synthesis filters of the filter bank. Simulations were done on the Daubechis wavelets with 12 coefficients and on complex valued wavelets. For the latter ones a real input sequence was used and split up into two subsequences in order to gain computational efficiency.

Network functions (NFs) such as network reflection and transmission coefficients are discussed about an interconnected network consisting of a lumped distributed N-port N non-commensurate line junction network (N-port) and a M-port. The derivation of the NFs can be done quite easily regardless of the complexity of the network by considering the flow of the traveling waves and conditions of the interconnected interface of the two multi-ports. The theory of this paper has been examined with respect to interconnected networks consisting of two 3-ports in both the time and frequency domains, and has shown good results consistent with other papers. The network functions described here can be used not only for the analysis of high-speed pulse propagation in digital systems with branches but also for the analysis of microwave distributed line networks such as hybird rings. In that sense, a new analysis method is presented in this paper.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.

In this paper, we propose a new FPGA design algorithm, Maple-opt, in which technology mapping, placement, and global routing are executed so that the delay of each critical signal path in an input circuit is within a specified upper bound imposed on it. The basic algorithm of Maple-opt is top-down hi-erarchical bi-partitioning of regions. Technology mapping onto logic-blocks of FPGAs, their placement, and global routing are determined simulatenously in each hierarchical process. This simultaneity leads to less congested layout for routing. In addition to that, Maple-opt computes a lower bound of delay for each path with a constraint value and determines critical paths based on the difference between the lower bound and the constraint value dynamically in each hierarchical process. Two delay reduction processes are executed for the critical paths; one is routing delay reduction and the other is logic-block delay reduction. Routing delay reduction is realized such that, when bi-partitioning a region, each constrained path is assigned to one subregion. Logic-block delay reduction is realized such that each constrained path is mapped onto fewer logic-blocks. Experimental results for some benchmark circuits show its efficiency and effectiveness.

A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm² with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.

This paper presents implicit representation of binary decision diagrams (implicit BDDs) as a new effecient data structure for Boolean functions. A well-known method of representing graphs by binary decision diagrams (BDDs) is applied to BDDs themselves. Namely, it is a BDD representation of BDDs. Regularity in the structure of BDDs representing certain Boolean functions contributes to significant reduction in size of the resulting implicit BDD repersentation. Since the implicit BDDs also provide canonical forms for Boolean functions, the equivalence of the two implicit BDD forms is decided in time proportional to the representation size. We also show an algorithm to maniqulate Boolean functions on this implicit data structure.

This article analyzes dynamics of the chaotic neural network and minimum searching principle of this network. First it is indicated that the dynamics of the chaotic newral network is described like a gradient decent, and the chaotic neural network can roughly find out a local minimum point of a quadratic function using its attractor. Secondly It is guaranteed that the vertex corresponding a local minimum point derived from the chaotic neural network has a lower value of the objective function. Then it is confirmed that the chaotic neural network can escape an invalid local minimum and find out a reasonable one.

This letter proposes evolutionary digital filters (EDFs) as new adaptive digital filters. The EDF is an adaptive filter which is controlled by adaptive algorithm based on the evolutionary strategies of living things. It consists of many linear/time-variant inner digital filters which correspond to individuals. The adaptive algorithm of the EDF controls and changes the coefficients of inner filters using the cloning method (the asexual reproduction method) or the mating method (the sexual reproduction method). Thus, the search algorithm of the EDF is a non-gradient and multi-point search algorithm. Numerical examples are given to show the effectiveness and features of the EDF such that they are not susceptible to local minimum in the multiple-peak performance surface.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

The power distribance appeared at a typical electric power system, which can be modeled by a simplified distributed circuit, is discussed. The electric power and the point where its power is injected are then estimated to suppress the power distrbance.

This letter proposes a pulse width modulated (PWM) control method which can stabilize chaotic orbits onto unstable fixed points and unstable periodic orbits. Some numerical experiments using the Lorenz equation show that chaotic orbits can be stabilized by the PWM control method. Furthermore, we investigate the stability in the neighborhood of an unstable fixed point and discuss the stability condition of the PWM control method.

A microphone array system with multi-stage processing for speech enhancement is presented in this paper. Two beamformers with uniform directional patterns, one aimed at the target source and the other at the interfering sources, convert the multi-channel inputs into two data sequences. A novel microphone array structure with a small aperture has been designed to obtain the dual beamformers. The outputs of the two beam-formers are then presented to a post-processing stage to further improve the quality and intelligibility of the speech signal. The post-processing stage can be selected from one of three different algorithms that are presented, which are suitable for different acoustic environments. Applications for such a system include hands-free telephony, teleconferencing and also special situations where speech signals must be picked up in an extremely noisy acoustic environment in which the microphones are hidden (e.g. in a forensic covert recording system).

We present a new method to cancel interfering sinusoidal signals. In this method, the Interpolated FFT (IpFFT) algorithm is used to estimate the parameters of the interference signal: frequency, amplitude and phase. The cancellation is then performed in the time domain. In order for the IpFFT to perform reliably, accurate spectral information about the interference signal is needed. Since, the information signal masks the interference signal, it becomes difficult to estimate the parameters of the interference signal. To alleviate this masking effect, two techniques are discussed here. These techniques involve frame update of interference spectral information of the interference signal, and adaptive averaging. Significant improvement over conventional frequency domain filterings is achieved. The price paid is only little, beyond the computation of the FFT. Comparison with the conventional frequency domain filter shows that our system has approximately 5dB better cancellation capability for a single interfering signal.

This paper proposes a tool to analyze complicated phenomena from a simple hysteresis network. The simple hysteresis network is described by a piecewise liner ordinal differential equation and has only two parameters: self feedback and DC team. Then this simple system exhibits various kinds of attractors: stable equilibria, periodic orbits, tori and chaos. In order to perform the numerical analysis, we derive return map and propose a fast calculation algorithm for the return map and its Lyapunov exponents based on the exact solutions. Using this algorithm, we have clarified chaos generation and related bifurcation phenomena. Also, we give theoretical formula that give fundamental bifurcation set.

G/D/1 is a theoretic model for ATM network queueing based on processing cells. We investigate the G/D/1 system by discrete time modeling. Takacs' combinatorial methods are applied to analyze the system performance. An approximation for the survivor function P[Q > q], which is the probability that the queue length Q in the stationary state exceeds q, is obtained. The obtained formula requires only very small computational complexity and gives good approximation for the true value of P[Q > q].