An intermediate frequency (IF) variable gain amplifier (VGA) with exponential gain control for a radio receiver is fabricated in 0.25-µm CMOS technology. The techniques to improve the bandwidth and to reduce temperature dependence of gain are described. The complete VGA is composed of two stages of linearized transconductance VGA and three stages of fixed gain amplifier (FGA). The complete VGA provides a continuous 10 dB to 76.5 dB gain control range, an IIP3 of -11.5 dBm and an NF of 15 dB at 40 MHz.

This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

This paper proposes a rail-to-rail OTA. By adding a signal decomposing circuit at the input of given OTAs that have a limited input voltage range, a rail-to-rail OTA is obtained. Each decomposed input voltage signal is converted to a current signal by an OTA and each output current of OTAs is summed to obtain a linear output signal. Since the input signal is decomposed into small magnitude voltage signals, the OTAs used to the voltage-current conversion do not require a wide input-range and any OTA can be used to realize a rail-to-rail input voltage range OTA. HSPICE simulations are performed to verify the validity of the proposed method.

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(V_GS-V_T)² even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

An active shield circuit which effectively reduces the substrate noise on the entire area inside the guard ring regardless of the noise source position is proposed. Simulation result shows that the proposed circuit can reduce the noise level to -85 dB while a conventional guard ring gives -52 dB.

A design optimization of active shield circuit using noise averaging method is proposed. The relation between the averaged noise and the design parameters of the active shield circuit such as circuit gain and on-chip layout is examined. A simple design guideline is also provided. Simulation results show that the active shield circuit designed by the proposed optimization method gives a better noise suppression performance of about 28% than the conventional one.

This paper presents an improved architecture of the multistage multibit sigma-delta modulators (ΣΔMs) for wide-band applications. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). Because of in-band zeros introduced by internal loop filters, the proposed architecture enhances the suppression of the in-band quantization noise at a low OSR. The HQCRFF-based modulator with single-bit quantizer has two modes of operation, modulation and oscillation. When the HQCRFF-based modulator is operating in oscillation mode, the feedback path from the quantizer output to the input summing node is disabled and hence the modulator output is free of the quantization noise terms. Although operating in oscillation mode is not allowed for single-stage ΣΔM, the oscillation of HQCRFF-based modulator can improve dynamic range (DR) of the multistage (MASH) ΣΔM. The key to improving DR is to use HQCRFF-based modulator in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. According to theoretical and numerical analysis, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.

This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.

This paper proposes a new controlling technique of asynchronous sigma delta modulation with characteristic of one-cycle response. This technique can reject power source perturbations in one cycle period and reduce the peaks of harmonic with one side random hysteresis technique. The proposed method was analyzed, designed, and experimented in a full bridge inverter. The distortion of output voltage and the harmonic peaks were used to measure the performance of the proposed technique. The experimental results show that the proposed technique can reduce the peak of harmonic up to 0.42 p.u and the harmonic distortion 5.9% at the ripple of 20% of power source when comparing with convention asynchronous sigma delta modulation.

A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-µm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/ over the temperature range from -100 to 150 at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.

This paper proposes a novel auto-reset forward DC-DC converter with inductor-switching technique to obtain the high performance by means of zero voltage switching and the fast transient response at steep load variations. The performance of the forward converter is strongly depending on the transformer reset-method. The Auto-reset method is used to recover the energy stored in leakage inductances of the transformer to the power supply and makes sure the zero voltage switching. Furthermore fast transient response is achieved by applying the inductor-switching technique, which keeps the output voltage constant in case of heavy burden load changes. The design of the proposed concept is verified by experiment of 12 V input and 1.8 V/12 A output.

In this paper, we propose the use of second-order slope compensation for a current-mode PWM buck converter. First, the current feedback loop in a current-mode PWM buck converter using a conventional slope compensation is analyzed by the small-signal transfer function. It becomes clear that the stability and frequency bandwidth of the current feedback loop is affected by the external input voltage and the output voltage of the converter. Next, the loop with second-order slope compensation is analyzed, and the result shows that the loop becomes unconditionally stable with the adoption of second-order slope compensation with appropriate parameter values and a current sensing circuit whose current is sensed across an impedance that is inversely proportional to the input voltage. In order to verify our theory, we designed whole circuits of a current-mode PWM buck converter including the new inductor current sensing circuit and the second-order voltage generator circuit using device parameters from the 0.6 µm CMOS process. The circuit simulation results under the conditions of 4 MHz switching frequency, 3.6 V input voltage and 2.4 V output voltage are presented.

Integrated 900-MHz ISM band transceiver LSI for analog cordless telephone has been realized by cost-effective process technology with sufficient performance. This LSI consisted of fully integrated transceiver, from RF-LNA to audio amplifier for RX chain, from microphone's amplifier to RF-PA for TX chain, and integrated RX- and TX-LO consisting of PLLs and VCOs. In view of narrow signal bandwidth with analog modulation, extremely low phase noise at low offset frequency from carrier was required for integrated VCO. Also, in view of fully duplex operations, signal isolation between TX and RX was required. Despite such a high integration and high performance, chip cost had to be minimized for low-cost applications. The 12-dB SINAD RX sensitivity was -111.2 dBm, the output power of TX was +3 dBm, and the phase noise of integrated VCO was -77 dBc/Hz at 3 kHz offset away from carrier. The current consumption at fully duplex operation was 76 mA at 3.6 V power supply. The chip was realized by 0.8 µm standard silicon BiCMOS process.

This paper presents a novel wide tuning range CMOS Voltage Controlled Oscillator (VCO). VCO uses an on-chip variable inductor as an additional variable element to extend the tuning range of VCO. The fabricated variable inductor achieves the variable range of 35%. The VCO was fabricated using 0.35 µm standard CMOS process, and can be tuned continuously from 2.13 GHz to 3.28 GHz (tuning range of 38%) without degradation of phase noise. Wide tunable LC-VCO using a variable inductor is one of the key circuits for reconfigurable RF circuit.

In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.

This paper presents the selective orthogonal matrix least-squares (SOM-LS) method for representing a multiport network characterized by sampled data with the rational matrix, improving the previous works, and providing new criteria. Recently, it is needed in a circuit design to evaluate physical effects of interconnects and package, and the evaluation is done by numerical electromagnetic analysis or measurement by network analyzer. Here, the SOM-LS method with the criteria will play an important role for generating the macromodels of interconnects and package in circuit simulation level. The accuracy of the macromodels is predictable and controllable, that is, the SOM-LS method fits the rational matrix to the sampled data, selecting the dominant poles of the rational matrix. In examples, simple PCB models are analyzed, where the rational matrices are described by Verilog-A, and some simulations are carried out on a commercial circuit simulator.

Projection-based model reductions become a necessity for efficient interconnect modeling and simulations. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the residual error of the transfer function can be considered as a stopping criteria to terminate the Arnoldi iteration process. Analytical expressions of this residual error are derived in detail. Furthermore, it can be found that the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves resultant vectors at the previous step of the Arnoldi algorithm. These error information will provide a guideline for the order selection scheme used in the Krylov subspace model-order algorithm.

Linear transformation transistor-only high-order current-mode filters are presented in this Letter. Based on the systematic design procedure, we can realize high-order current-mode filters employing switched-current technique efficiently. Only two kinds of switched-current basic cells are needed in our design to obtain simple architectures. The fifth-order Chebychev lowpass filter is designed to verify the proposed synthesis method. Simulation results that confirm the theoretical analysis are obtained.

This paper proposes a new robust adaptive processing algorithm that is based on the extended least squares (ELS) method with running spectrum filtering (RSF). By utilizing the different characteristics of running spectra between speech signals and noise signals, RSF can retain speech characteristics while noise is effectively reduced. Then, by using ELS, autoregressive moving average (ARMA) parameters can be estimated accurately. In experiments on real speech contaminated by white Gaussian noise and factory noise, we found that the method we propose offered spectrum estimates that were robust against additive noise.

This paper presents a new framework for traffic flow control based on an integrated model description by means of Hybrid Dynamical System (HDS). The geometrical information on the traffic network is characterized by Hybrid Petri Net (HPN). Then, the algebraic behavior of traffic flow is transformed into Mixed Logical Dynamical Systems (MLDS) form in order to introduce an optimization technique. These expressions involve both continuous evolution of traffic flow and event driven behavior of traffic signal. HPN allows us to easily formulate the problem for complicated and large-scale traffic network due to its graphical understanding. MLDS enables us to optimize the control policy for traffic signal by means of its algebraic manipulability and use of model predictive control framework. Since the behavior represented by HPN can be directly transformed into corresponding MLDS form, the seamless incorporation of two different modeling schemes provide a systematic design scenario for traffic flow control.

This paper presents pulse-coupled two bifurcating neurons. The single neuron is represented by a spike position map and the coupled neurons can be represented by a composition of the spike position maps. Using the composite map, we can analyze basic bifurcation phenomena and can find some interesting phenomena that are caused by the pulse-coupling and are impossible in the single neuron. Presenting a simple test circuit, typical phenomena are confirmed experimentally.

The complete subtree (CS) method is widely accepted for the broadcast encryption. A new method for assigning keys in the CS method is proposed in this paper. The essential idea behind the proposed method is to use two trapdoor permutations. Using the trapdoor information, the key management center computes and assigns a key to each terminal so that the terminal can derive all information necessary in the CS method. A terminal has to keep just one key, while log₂ N + 1 keys were needed in the original CS method where N is the number of all terminals. The permutations to be used need to satisfy a certain property which is similar to but slightly different from the claw-free property. The needed property, named strongly semi-claw-free property, is formalized in terms of probabilistic polynomial time algorithm, and its relation to the claw-free property is discussed. It is also shown that if the used permutations fulfill the strongly semi-claw-free property, then the proposed method is secure against attacks of malicious users.

The paper first researches the properties of neural networks in the framework of the dual linear programming theory, then discusses the variation range of a Hessian matrix associated to dual linear programming problems. By means of eigenvalues method, a Lipschitz constant based formula for determining the algorithm step-size is presented. Two examples are given to show that the proposed formula is efficacious.

This paper proposes an algorithm to improve the performance of the noise power spectrum estimation using the minimum statistics (MS). The minimum statistics noise estimator (MSNE) that is most efficient for speech enhancement often underestimates noise power when the signal characteristics changes abruptly. The proposed algorithm improves the accuracy of noise estimation by removing harmonic components of the speech signal. Simulation results verify that the performance of the proposed algorithm is better than that of the conventional algorithm in terms of the segmental SNR (SegSNR) and the spectral distance (SD).

An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating polynomial. To implement a compression characteristic in a digital audio system, a power calculation with fractional numbers is required and it is difficult to be performed directly in digital circuits. We introduce a polynomial expression to approximate the power operation, then the gain calculation is easily performed with a number of additions, multiplications and a division. Newton's interpolation formula is used to calculate the compression characteristics in a very short time and the obtained compression characteristics are very close to the ideal ones.

Optimum wideband beam pattern synthesis methods are usually sensitive to antenna elements gain, phase and position errors. In this letter, these errors are taken into account in a constraint optimization process, and a generalized diagonal loading algorithm is obtained. Computer simulations indicate the robustness of this new method.

A noise reduction technique to reduce background noise in noisy speech is proposed. We have proposed the noise reduction method which uses a noise reconstruction system. However, since a residual speech signal is included in the input signal of a noise reconstruction filter (NRF) used for reconstructing the background noise, the long time average value of error signal for estimating the background noise is needed not to estimate the speech signal. Therefore, the ability of tracking the non-stationary noise is decreased. In order to solve this problem, we propose the noise reconstruction system with adaptive line enhancer (ALE). Since ALE works to obtain the signal occupied by noise components, the input signal of the NRF includes only a few speech components. Therefore, we can give the high tracking ability to NRF.

A combining method for receiver diversity, followed by a Bayesian decision feedback equalizer, is proposed. This eigenvector based combining maximizes the desired part energy of combined channel, on which the equalizer performance mainly depends. The validity of the proposed method is demonstrated by simulations.

Recently Azou et al. proposed a method of model reduction for discrete systems based on a new impulse response Gramian. The reduced model was derived by first approximating the low-order impulse response Gramian, and then matching some Markov parameters and time-moments of an original model. In this note a modified method is presented so that the reduced model exactly preserves the low-order impulse response Gramian together with a slightly different set of Markov parameters and time-moments of the original model.

In this letter, we provide a solution to the stabilization problem of a class of Lipschitz nonlinear systems by output feedback. Via the newly proposed nonlinearity characterization function (NCF) concept, we propose an effective method in designing an output feedback controller. Under the suggested sufficient condition which is derived by using the NCF, the proposed control scheme achieves the global exponential stabilization.

The facility layout problem is one of the most fundamental quadratic assignment problems in operations research. In this paper, we present an improved genetic algorithm for solving the facility layout problem. In our computational model, we propose several improvements to the basic genetic procedures including conditional crossover and mutation. The performance of the proposed method is evaluated on some benchmark problems. Computational results showed that the improved genetic algorithm is capable of producing high-quality solutions.

Recently, Boneh et al. proposed provably secure short signature schemes in the standard model and in the random oracle model respectively. In this letter, we propose strong-key substitution attacks on these signature schemes. In one of the attacks, we show that an adversary can generate a new public key satisfying all legitimate signatures created by the legitimate signer.